Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms

Journal of Systems Architecture

Volumn 56, Issue 7, 2010, Pages 242-255

  Singh, Amit Kumar ^a   Srikanthan, Thambipillai ^a   Kumar, Akash ^b,c   Jigang, Wu ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Hardware software co design; Heterogeneous architectures; Mapping algorithms; MPSoC design; Network on Chip (NoC)

Indexed keywords

HARDWARE SOFTWARE CODESIGN; HETEROGENEOUS ARCHITECTURES; MAPPING ALGORITHMS; MPSOC DESIGN; NETWORK ON CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONFORMAL MAPPING; DESIGN; ENERGY CONSERVATION; ENERGY UTILIZATION; NETWORK ARCHITECTURE; SERVERS; VLSI CIRCUITS; VOLTAGE CONTROL;

MULTIPROCESSING SYSTEMS;

EID: 77955717866     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2010.04.007     Document Type: Article

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