-
1
-
-
84948696213
-
A Network on Chip Architecture and Design Methodology
-
Pittsburgh, USA, pp, April
-
S. Kumar, A. Jantsch, M. Miliberg, J. Oberg, J.-P. Soininen, M. Forseli, K. Tiensyrja, and A. Hemani, "A Network on Chip Architecture and Design Methodology," in Proc. ISVLSI'02, Pittsburgh, USA, pp. 105-112, April 2002.
-
(2002)
Proc. ISVLSI'02
, pp. 105-112
-
-
Kumar, S.1
Jantsch, A.2
Miliberg, M.3
Oberg, J.4
Soininen, J.-P.5
Forseli, M.6
Tiensyrja, K.7
Hemani, A.8
-
2
-
-
84893687806
-
A Generic Architecture for On-chip Packet Switched Interconnections
-
Paris, France, pp, March
-
P. Guerrier and A. Greiner, "A Generic Architecture for On-chip Packet Switched Interconnections," in Proc. DATE 2000, Paris, France, pp. 250-256, March 2000.
-
(2000)
Proc. DATE
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
3
-
-
46449119799
-
-
S. Saeidi, A. Khademzadeh, and A. Mehran, SMAP: An Intelligent Mapping Tool for Network on Chip, to be presented at ISSCS 2007, PID360581, Iasi, Romania, July 2007.
-
S. Saeidi, A. Khademzadeh, and A. Mehran, "SMAP: An Intelligent Mapping Tool for Network on Chip," to be presented at ISSCS 2007, PID360581, Iasi, Romania, July 2007.
-
-
-
-
4
-
-
27644494723
-
Key Research Problems in NoC Design: A Holistic Perspective
-
New Jersey, USA, pp, Sept. 19-21
-
Umit Y. Ogras and J. Hu, "Key Research Problems in NoC Design: A Holistic Perspective," in Proc. CODES+ISSS'05, New Jersey, USA, pp. 69-74, Sept. 19-21, 2005.
-
(2005)
Proc. CODES+ISSS'05
, pp. 69-74
-
-
Ogras, U.Y.1
Hu, J.2
-
5
-
-
84954421164
-
Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints
-
Jan
-
J. Hu and R. Marculescu, "Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints," in Proc. ASP-DAC'03, pp. 233-239, Jan. 2003.
-
(2003)
Proc. ASP-DAC'03
, pp. 233-239
-
-
Hu, J.1
Marculescu, R.2
-
6
-
-
34548569239
-
Spiral: Spiral: A Heuristic Mapping Algorithm for Network on Chip
-
Aug
-
A. Mehran, S. Saedi, A. Khademzadeh, and K. Badie, "Spiral: Spiral: A Heuristic Mapping Algorithm for Network on Chip," IEICE Electron. Exp., vol. 4, no. 15, pp. 478-484, Aug. 2007.
-
(2007)
IEICE Electron. Exp
, vol.4
, Issue.15
, pp. 478-484
-
-
Mehran, A.1
Saedi, S.2
Khademzadeh, A.3
Badie, K.4
-
7
-
-
84944322013
-
A Two-step Genetic Algorithm for Mapping Task Graphs to Network on Chip Architecture
-
Sept
-
T. Lei and S. Kumar, "A Two-step Genetic Algorithm for Mapping Task Graphs to Network on Chip Architecture," in Proc. DSD'03, pp. 180-187, Sept. 2003.
-
(2003)
Proc. DSD'03
, pp. 180-187
-
-
Lei, T.1
Kumar, S.2
-
8
-
-
34548717064
-
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
-
May
-
E. Carvalho, N. Calazans, and Fernado Moraes, "Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs," in 18th IEEE/IFIP International Workshop on Rapid System. Prototyping (RSA 2007), pp. 34-40, May 2007.
-
(2007)
18th IEEE/IFIP International Workshop on Rapid System. Prototyping (RSA
, pp. 34-40
-
-
Carvalho, E.1
Calazans, N.2
Moraes, F.3
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