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Volumn , Issue , 2004, Pages 421-424
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Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
COMPUTER ARCHITECTURE;
ENERGY UTILIZATION;
INTEGRATED CIRCUIT LAYOUT;
MAPPING;
MICROPROCESSOR CHIPS;
PROGRAM PROCESSORS;
QUALITY OF SERVICE;
CHIP ARCHITECTURE;
RECONFIGURABLE TILED SYSTEMS;
RUN-TIME MAPPING;
SYSTEM ON CHIP (SOC);
FIELD PROGRAMMABLE GATE ARRAYS;
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EID: 20844442766
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (33)
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References (5)
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