Congestion-aware task mapping in heterogeneous MPSoCs

2008 International Symposium on System-on-Chip Proceedings, SOC 2008

Volumn , Issue , 2008, Pages

  Carvalho, Ewerson ^a   Moraes, Fernando ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL LOADS; CONGESTION-AWARE; DYNAMIC TASKS; MAPPING ALGORITHMS; PACKET LATENCIES; PROGRAMMABLE PROCESSORS; RUNNING-IN; SILICON TECHNOLOGIES; SOC DESIGNS; STATIC MAPPING; SYSTEMS ON CHIPS; TASK MAPPING; VLSI DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

MULTIPROCESSING SYSTEMS;

EID: 67249085600     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2008.4694878     Document Type: Conference Paper

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