Cell multiprocessor communication network: Built for speed

IEEE Micro

Volumn 26, Issue 3, 2006, Pages 10-23

  Kistler, Michael ^a   Perrone, Michael ^b   Petrini, Fabrizio ^c  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c PACIFIC NORTHWEST NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA-PERFORMANCE; CELL MULTIPROCESSOR; MULTICORE PROCESSOR DESIGN; ON-CHIP COMMUNICATION NETWORK; POWER-PERFORMANCE;

BENCHMARKING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAM PROCESSORS; SYNCHRONIZATION;

NETWORK PROTOCOLS;

EID: 33746923043     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2006.49     Document Type: Article

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