Dynamic task allocation strategies in MPSoC for soft real-time applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1386-1389

  Brião, Eduardo Wenzel ^a   Barcelos, Daniel ^a   Wagner, Flávio Rech ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BINS; ELECTRIC LOAD FORECASTING; ENERGY CONSERVATION; ENERGY POLICY; FAULT TOLERANCE; INDUSTRIAL ENGINEERING; QUALITY ASSURANCE; REAL TIME SYSTEMS; RELIABILITY; TESTING;

BIN-PACKING; DESTINATION NODES; DYNAMIC TASK ALLOCATION; DYNAMIC VOLTAGE SCALING; ENERGY CONSUMPTION; LINEAR CLUSTERING; MULTIPROCESSOR SYSTEMS ON CHIPS; SAVE ENERGY; SOFT REAL-TIME APPLICATIONS; SYSTEM ENERGY; TASK ALLOCATION; TASK MIGRATION; TWO TYPES;

CLUSTERING ALGORITHMS;

EID: 49749088883     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484934     Document Type: Conference Paper

References (13)

1. R.Bergamaschi, W.Lee. "Designing System-on-Chip using Cores". In: 37 th Design Automation Conference (DAC), USA, 2000, pp. 420-425.
2. L.Benini, G.DeMicheli. "Networks on chips: a new SoC paradigm". IEEE Computer, vol.35, n.1, pp. 70-78. 2002.
3. A.Gerasoulis, T.Yang. "On the Granularity and Clustering of Directed Acyclic Task Graphs". IEEE Trans. Parallel Distrib. Syst., v.4, n.6,. 1993. pp. 686-701
4. D.Johnson. Near-optimal Bin-packing Algorithms. Cambridge, Mass. 1973
5. S.Bertozzi, A.Acquaviva, D.Bertozzi, A.Poggiali. "Supporting Task Migration in Multi-processor Systems-on-chip: a Feasibility Study". In: Design, Automation and Test in Europe Conference (DATE), Munich, Germany, 2006, pp. 15-20.
6. F.Wronski, E.Brião, F.R.Wagner. "Evaluating Energy-Aware Task Allocation Strategies for MPSoCs". In: IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES). Braga, Portugal, October 2006.
7. H.Wang. "Orion: A Power-performance Simulator for Interconnection Networks". In: ACM MICRO. Istanbul, Turkey,. 2002. pp. 294-305
8. J.Butts, G.Shoi. "A Static Power Model for Architects". In: International Symposium on Microarchitecture, ACM Press, California, 2000, pp. 191-201.
9. S.A. Ito; L. Carro; R.P. Jacobi. "Making Java Work for Microcontroller Applications". IEEE Design & Test of Computers vol 18, Issue 5, 2001, pp. 100-110.
10. C.Zeferino, A.Susin. "SoCIN: a Parametric and Scalable Network-on-Chip". In: Symposium on Integrated Circuits and Systems Design (SBCCI), 2003, pp.169-174.
11. A. Beck, J. Mattos,; F. Wagner; L. Carro. "CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator". In: Symposium On Integrated Circuits And Systems Design, 2003, São Paulo, Brasil. IEEE Computer Society Press, 2003. p.349-354.
12. J. Zhuo, and C. Chakrabarti. "An Efficient Dynamic Task Scheduling Algorithm for Battery Powered DVS Systems" In: Design Automation Conference Asia and South Pacific (ASPDAC), 2005, pp.846-849.
13. EEMBC. The Embedded Microprocessor Benchmark Consortium. http://www.eembc.org 2006.