A 56mW CT quadrature cascaded ΣΔ modulator with 77dB DR in a near zero-IF 20MHz band

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 238-240

  Breems, Lucien J ^a   Rutten, Robert ^a   Van Veldhoven, Robert ^a   Van Der Weide, Gerard ^a   Termeer, Henk ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL FILTERS; FREQUENCY BANDS; MODULATORS; PROGRAMMABLE LOGIC CONTROLLERS; SIGNAL RECEIVERS;

DIGITAL QUADRATURE NOISE-CANCELLATION FILTER; WIDEBAND RECEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 34548817840     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373382     Document Type: Conference Paper

References (4)

1. G. Mitteregger, C. Ebner, S. Mechnig, et al., "A 14b 20mW 640MHz CMOS CT ΣΔ ADC with 20MHz Signal Bandwidth and 12b ENOB," ISSCC Dig. Tech. Papers, pp. 62-63, Feb., 2006.
2. R. Schreier, N. Abaskharoun, H. Shibata, et al., "A375mW Quadrature Bandpass ΣΔ ADC with 90dB DR and 8.5.MHz BW at 44MHz," ISSCC Dig. Tech. Papers, pp. 64-65, Feb., 2006.
3. R. Rutten, L. J. Breems, G. Wetzker, "Digital Calibration of a Continuous-Time Cascaded ΣΔ Modulator based on Variance Derivative Estimation," Proc. ESSCIRC, pp. 199-202, Sep., 2006.
4. S. A. Jantzi, K. W. Martin, A. S. Sodra, "Quadrature Bandpass ΣΔ Modulation for Digital Radio," IEEE J. Solid-State Circuits, vol. 32, pp. 1935-1950, Dec., 1997.