A 65nm CMOS CT ΔΣ modulator with 81dB DR and 8MHz BW auto-tuned by pulse injection

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 500-502

  Shu, Yun Shiang ^a   Song, Bang Sup ^a   Bacrania, Kantilal ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b RF/MS Design Group   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

65NM CMOS; DELTA SIGMA MODULATOR; FULL-SCALE RANGES; LMS ALGORITHMS; NULLING; PULSE INJECTION;

MODULATORS;

EID: 49549124516     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523276     Document Type: Conference Paper

References (3)

1. G. Mitteregger, C. Ebner, S. Mechnig, et al., "A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB," ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 2006.
2. L. J. Breems, R. Rutten, R. van Veldhoven, et al., "A 56mW CT Quadrature Cacaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2007.
3. P. Kiss, J. Silva, A. Wiesbauer, et al., "Adaptive Digital Correction of Analog Errors in MASH ADC's-Part II: Correction Using Test-Signal Injection," IEEE Trans. Circuits Syst. II, vol. 47, pp. 629-638, Jul. 2000.