A continuous-time ΣΔ modulator with reduced sensitivity to clock jitter through SCR feedback

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 5, 2005, Pages 875-884

  Ortmanns, Maurits ^a   Gerfers, Friedel ^b   Manoli, Yiannos ^c  

^a Sci worx GmbH   (Germany)

^b NXP SEMICONDUCTORS   (Netherlands)

^c UNIVERSITY OF FREIBURG   (Germany)

Author keywords

Clock jitter; Continuous time (CT); Sigma delta ( ) modulator; Switched capacitor resistor (SCR) feedback

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; ELECTRIC FILTERS; JITTER; MODULATORS; RESISTORS;

CLOCK JITTER; CONTINUOUS TIME (CT) MODULATORS; SWITCHED CAPACITOR RESISTOR (SCR) FEEDBACK;

DELTA SIGMA MODULATION;

EID: 20144368296     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.846227     Document Type: Article

References (21)

1. E. J. van der Zwan and E. C. Dijkmans, "A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1873-1880, Dec. 1996.
2. F. Gerfers, M. Ortmanns, and Y. Manoli, "A 1.5-V, 12-bit power efficient continuous-time third-order ΣΔ modulator," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1343-1352, Aug. 2003.
3. J. A. Cherry and W. M. Snelgrove, "Excess loop delay in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., Analog Digit. Signal Process., vol. 46, no. 4, pp. 376-389, Apr. 1999.
4. J. A. Cherry and W. M. Snelgrove, "Clock jitter and quantizer metastability in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 6, pp. 661-676, Jun. 1999.
5. H. Tao, L. Toth, and J. M. Khoury, "Analysis of timing jitter in bandpass sigma-delta modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 8, pp. 991-1001, Aug. 1999.
6. M. Ortmanns, F. Gerfers, and Y. Manoli, "Jitter insensitive feedback DAC for continuous-time ΣΔ modulators," in Proc. IEEE Int. Conf. Electronics, Circuits, and Systems, 2001, pp. 1049-1052.
7. O. Oliaei and H. Aboushady, "Jitter effects in continuous time ΣΔ modulators with delayed return-to-zero feedback," in Proc. Int. Conf. Electronics, Circuits, and Systems, Sep. 1998, pp. 351-354.
8. M. Ortmanns, F. Gerfers, and Y. Manoli, "A continuous-time ΣΔ modulator with reduced jitter sensitivity," in Proc. Eur. Solid-State Circuits Conf., 2002, pp. 287-290.
9. A. Berkovitz and I. Rusnak, "FFT processing of randomly sampled harmonic signals," IEEE Trans. Signal Process., vol. 40, no. 11, pp. 2816-2819, Nov. 1992.
10. M. Ortmanns, F. Gerfers, and Y. Manoli, "Fundamental limits of insensitivity in discrete and continuous-time ΣΔ modulators," in Proc. IEEE Int. Symp. on Circuits and Systems, 2003.
11. L. Doerrer, "A 10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 um CMOS process," in Proc. Eur. Solid-State Circuits Conf., 2003.
12. S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters. New York: IEEE Press, 1997.
13. A. Marques, V. Peluso, M. S. Steyaert, and W. M. Sansen, "Optimal parameters for AS modulators topologies," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 9, pp. 1232-1241, Sep. 1998.
14. O. Oliaei, "Design of continuous-time sigma-delta modulators with arbitrary feedback waveform," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 8, pp. 437-444, Aug. 2003.
15. G. Gielen, K. Francken, E. Martens, and M. Vogels, "An analytical integration method for the simulation of continuous-time ΣΔ modulators," IEEE Trans. Computer-Aided Design, vol. 23, no. 3, pp. 389-399, Mar. 2004.
16. M. Ortmanns, F. Gerfers, and Y. Manoli, "Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 51, no. 6, pp. 1088-1100, Jun. 2004.
17. M. Ortmanns, F. Gerfers, and Y. Manoli, "Influence of finite integrator gain bandwidth on CT sigma delta modulators," in Proc. IEEE Int. Symp. on Circuits and Systems, 2003.
18. F. Medeiro, B. Perez-Verdu, and A. Rodriguez-Vazquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Norwell, MA: Kluwer, 1999.
19. R. van Veldhoven, "Triple-mode continuous-time Σmodulator with switched-capacitor feedback DAC for GSM-EDGE/CDMA2000/UMTS receiver," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2069-2076, Dec. 2003.
20. M. Ortmanns, F. Gerfers, and Y. Manoli, "A continuous-time ΣΔ modulator with switched capacitor controlled current mode feedback," in Proc. Eur. Solid-State Circuits Conf., 2003.
21. S. Luschas and H.-S. Lee, "High-speed Σmodulators with reduced timing jitter sensitivity," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 11, pp. 712-720, Nov. 2002.