A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded ΣΔ modulator

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 796-804

  Kulchycki, Scott D ^a,b,c   Trofin, Roxana ^a,b   Vleugels, Katelijn ^a,b   Wooley, Bruce A ^a,b  

^a IEEE

^b Stanford University   (United States)

^c NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

Analog to digital (A D) conversion; Broadband analog to digital converter (ADC); Cascaded modulator; Continuous time (CT) modulator; High resolution ADC

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; DELTA SIGMA MODULATION; ENERGY DISSIPATION;

ANALOG SUPPLY;

MODULATORS;

EID: 41549098703     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917499     Document Type: Conference Paper

References (26)

1. J.C. Candy, "A use of double integration in sigma-delta modulation," IEEE Trans. Commun., vol. COM-33, no. 3, pp. 249-258, Mar. 1985.
2. T. Burger and Q. Huang, "A 13.5-mW 185-Msamples/s ΔΣ modulator for UMTS/GSM dual-standard IF reception," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1868-1878, Dec. 2001.
3. T. Salo, S. Lindfors, T. Hollman, J. Jarvinen, and K. Halonen, "80-MHz bandpass SA modulators for multimode digital IF receivers," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 464-474, Mar. 2003.
4. J. Vink and J. van Rens, "A CMOS multi-bit sigma-delta modulator for video applications," in Proc. Eur: Solid-State Circuits Conf., 1988, pp. 164-167.
5. L. J. Breems, R. Rutten, and G. Wetzker, "A cascaded continuoustime SD modulator with 67-dB dynamic range in 10-MHz bandwidth," IEEE J. Solid-States Circuits, vol. 39, no. 12, pp. 2152-2160, Dec. 2004.
6. R. Schoofs, M. S. J. Steyaert, and W. M. C. Sansen, "A design-optimized continuous-time delta-sigma ADC for WLAN applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 1, pp. 209-217, Jan. 2007.
7. A. Di Giandomenico, S. Paton, A. Wiesbauer, L. Hernandez, T. Potscher, and L. Dorrer, "A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13 μm. CMOS," in Proc. Eur: Solid-State Circuits Conf., 2003, pp. 233-236.
8. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, "A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwdith, 80-dB dynamic range and 12-bit ENOB," IEEE J. Solid-State Circuits, vol. 4.1, no. 12, pp. 2641-2649, Dec. 2006.
9. S. D. Kulchycki, R. Trofin, K. Vleugels, and B. A. Wooley, "A 1.2-V 77-dB 7.5-MHz continuous-time/discrete-time cascaded SD modulator," in Symp. VLSI Circuits Dig. Tech. Papers, 2007, pp. 238-239.
10. B. Brandt, D. Wingard, and B. Wooley, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 618-627, Apr. 1991.
11. M. Rebeschini, "The design of cascaded ΔΣ ADCs," in Delta-Sigma Data Converters, S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds. Piscataway, NJ: IEEE Press, 1997, pp. 193-218.
12. E. van der Zwan and E. C. Djikmans, "A 0.2 mW CMOS Σ-Δ modulator for speech coding with 80 dB dynamic range," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1873-1880, Dec. 1996.
13. L. A. Williams and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 193-202, Mar. 1994.
14. G. Vemulapalli, P. Hanumolu, Y.-J. Kook, and U.-K. Moon, "A 0.8-V accurately tuned linear continuous-time filter," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1972-1977, Sep. 2005.
15. J. F. Jensen, G. Raghavan, A. E. Cosand, and R. H. Walden, "A 3.2-GHz, second-order delta-sigma modulator implemented in InP HBT technology," IEEE J. Solid-State Circuits, vol. 30, no. 10, pp. 1119-1127, Oct. 1995.
16. J. Cherry and W. Snelgrove, "Excess loop delay in continuous-time delta-sigma modulators," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 4, pp. 376-389, Apr. 1999.
17. P. Benabes, M. Keramat, and T. Kielbasa, "A methodology for designing continuous-timesigma-deltamodulators,"in Proc. Eur. Design and Test Conf., 1997, pp. 46-50.
18. S. Yan and E. Sanchez-Sinencio, "A continuous-time ΣΔ modulator with 88 dB dynamic range and 1.1 MHz signal bandwidth," in IEEE ISSCC Dig. Tech. Papers, 2003, vol. 1, pp. 62-478.
19. B. P. Del Signore, D. A. Kerth, N. S. Sooch, and E. J. Swanson, "A monolithic 20-b delta-sigma A/D converter," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1311-1317, Dec. 1990.
20. B. Putter, "A 5th order CT/DT multi-mode ΔΣ modulator," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 244-245.
21. C. L. Phillips and R. D. Harbor, Feedback Control Systems, 4th. ed. Upper Saddle River, NJ: Prentice-Hall, 1999.
22. R. Schreier and B. Zhang, "Delta-sigma modulators employing continuous-time circuitry," IEEE Trans. Circuits Sys. I, Fundam. Theory Appl., vol. 43, no. 4, pp. 324-332, Apr. 1996.
23. K. Vleugels, "Broadband oversampling analog-to-digital conversion for digital communications," Ph.D. dissertation, Dept. Elect. Eng., Stanford Univ., Stanford, CA, 2002.
24. B. Razavi, Data Conversion System Design. Piscataway, NJ: IEEE Press, 1995.
25. S. Limotyrakis, "Power-efficient broadband A/D conversion," Ph.D. dissertation, Dept. Elect. Eng., Stanford Univ., Stanford, CA, 2004.
26. D. Barkin, "Bandpass digital-to-analog conversion for wireless applications," Ph.D. dissertation, Dept. Elect. Eng., Stanford Univ., Stanford, CA, 2004.