A 14 bit continuous-time delta-sigma A/D modulator with 2.5 MHz signal bandwidth

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 9, 2007, Pages 1873-1883

  Li, Zhimin ^b   Fiez, Terri S ^a,c  

^a IEEE

^b SILICON LABORATORIES   (United States)

^c 1148 Kelley Engineering Center Corvallis   (United States)

Author keywords

Analog to digital converter; Continuous time; Current calibration; Delta sigma

Indexed keywords

BANDWIDTH; CALIBRATION; CMOS INTEGRATED CIRCUITS; JITTER; OPTICAL RESOLVING POWER;

CURRENT CALIBRATION; DELTA-SIGMA;

ANALOG TO DIGITAL CONVERSION;

EID: 34548289295     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.903086     Document Type: Conference Paper

References (22)

1. K. Nam, S-M. Lee, D. K. Su, and B. A. Wooley, "A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1855-1864, Sep. 2005.
2. T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro, and S. W. Harston, "A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1896-1906, Dec. 1997.
3. R. Jiang and T. Fiez, "A 14-bit delta-sigma ADC with 8X OSR and 4-MHz conversion bandwidth in A 0.18 μm CMOS process," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 63-74, Jan. 2004.
4. A. Bosi, A. Panigada, G. Cesura, and R. Castello, "An 80 MHz 4× oversampled cascaded ΔΣ-pipelined ADC with 75 dB DR and 87 dB SFDR," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 174-175.
5. L.J. Breems, E. J. van der Zwan, and J. H. Huijsing,"A 1.9-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion, of IF signals," IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 468-475, Apr. 2000.
6. R. van Veldhoven, "A tri-mode continuous-Time ΣΔ modulator with, switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/ UMTS receiver," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 60-61.
7. A. Das, R. Hezar, R. Bryd, G. Gomez, and B. Haroun, "A 4th-order 86 dB CT ΔΣ ADC with two amplifiers in 90 mm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 496-497.
8. R. van Veldhoven, K. Philips, and B. Minnis, "A 3.3 mW ΣΔ modulator for UMTS in 0.18 μm CMOS with 70dB dynamic range in 2 MHz bandwidth," in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 222-223.
9. M. S. Kappes, "A 2.2-mW CMOS bandpass continuous-time multibit Δ Σ ADC with 68 dB of dynamic range and 1-MHz bandpass for wireless applications," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1098-2003, Jul. 2003.
10. T. Ueno and T. Itakura, "A 0.9 V 1.5 mW continuous-time ΣΔ modulator for WCDMA," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 78-79.
11. L. Dorrer, F. Kuttner, P. Greco, and S. Derksen, "A 3 mW 74 dB SNR 2 MHz CT ΔΣ ADC with a tracking-ADC-quantizer in a 0.13 μm CMOS," in IEEE ISSCCDig. Tech. Papers, 2005, pp. 492-493.
12. N. Yaghini and D. Johns, "A 43 mW CT Complex ΔΣ ADC with 23 MHz of Signal bandwidth and 68.8 dB SNDR.," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 501-502.
13. S. Yan and E. Sanchez-Sinencio, "A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1 -MHz signal bandwidth," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 75-86, Jan. 2004.
14. ADS 1605/1606 datasheet Texas Instruments, Inc., Nov. 2003.
15. F. M. Gardner, "A transformation for digital simulation of analog filters," IEEE Trans. Commun., pp. 676-680, Jul. 1986.
16. J. A. Cherry and W. M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion, Theory, Practice and Fundamental Performance Limits. Norwell, MA: Kluwer Academic, 2000.
17. S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation. New York: IEEE Press, 1997.
18. D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C A. A. Bastiaansen, "A self-calibration technique for monlithic high-resolution D/A converters," IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1517-1522, Dec. 1989.
19. K. Falakshahi, C.-K. K. Yang, and B. A. Wooley, "A 14-bit, 10-Msamples/sec digital-to-analog converter using multi-bit sigma-delta modulation," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 607-615, May 1999.
20. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.
21. Z. Y. Chang, D. Haspeslagh, and J. Verfaule, "A highly linear CMOS Gm-C bandpass filter with on-chip frequency tuning," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 388-397, Mar. 1997.
22. Y. Cong and R. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," IEEE Trans. Circuits Syst. II, vol. 47, no. 7, pp. 585-595, Jul. 2000.