A 500kHz-10MHz multimode power-performance scalable 83-to-67dB DR CTδσ in 90 nm digital CMOS with flexible analog core circuitry

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 70-71

  Crombez, Pieter ^a,b   Van Der Plas, Geert ^a   Steyaert, Michiel ^b   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b Dept ESAT MICAS ^*  (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ANALOG CORES; BUILDING BLOCKES; CONTINUOUS TIME; DIGITAL CMOS; MULTIMODES; POWER CONSUMPTION;

ELECTRIC POWER UTILIZATION; WIRELESS LOCAL AREA NETWORKS (WLAN);

VLSI CIRCUITS;

EID: 70449411603     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. R. van Veldhoven, "A Triple-Mode Continuous-Time σδ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver", IEEE J. Solid-State circuits, vol. 38, pp. 2069-2076, Dec. 2003.
2. J. Arias et al., "A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers", IEEE J. Solid-State circuits, vol. 41, pp. 339-351, Feb. 2006.
3. M. Vadipour et al., "A 2.1mW/3.2mW Delay-Compensated GSM/WCDMA Sigma-Delta Analog-Digital Converter", IEEE Symp. VLSI Circuits, Dig. Tech. Papers, pp. 180-181, Jun. 2008.
4. S. Ouzounov et al., "A 1.2V 121-Mode CT Delta-Sigma Modulator for Wireless Receivers in 90nm CMOS", ISSCC Dig. Tech. Papers, pp. 242-243, Feb. 2007.