Performance optimization for gridded-layout standard cells

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5567, Issue PART 1, 2004, Pages 107-118

  Wang, Jun ^a   Wong, Alfred K ^b   Lam, Edmund Y ^a  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

^b Fortis Systems Inc   (United States)

Author keywords

Circuit performance; Design for manufacturability (DFM); Design rules; Gridded layout; Leakage current; Low k1 lithography; MOSFETs scaling; Multiple exposures; Resolution Enhancement Techniques (RETs); Standard cells; Template lithography

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COSTS; DIFFRACTION; LEAKAGE CURRENTS; LITHOGRAPHY; OPTIMIZATION; PHASE SHIFT;

CIRCUIT PERFORMANCE; DESIGN FOR MANUFACTURABILITY (DEM); DESIGN RULES; GRIDDED LAYOUT; LOW-K1 LITHOGRAPHY; MOSFETS SCALING; MULTIPLE EXPOSURES; RESOLUTION ENHANCEMENT TECHNIQUES (RET); STANDARD CELLS; TEMPLATE LITHOGRAPHY;

MOSFET DEVICES;

EID: 19844378577     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.569398     Document Type: Conference Paper

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