High-performance circuit design for the RET-enabled 65nm technology node

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5379, Issue , 2004, Pages 20-29

  Liebmann, Lars ^a   Barish, Arnold ^c   Baum, Zachary ^a   Bonges, Henry ^a   Bukofsky, Scott ^a   Fonseca, Carlos ^a   Halle, Scott ^a   Northrop, Greg ^b   Runyon, Steve ^c   Sigal, Leon ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

^c IBM   (United States)

Author keywords

Layout optimization; Radical design restrictions (RDR); Resolution enhancement techniques (RET)

Indexed keywords

DESIGN FLOW; LAYOUT OPTIMIZATION; RADICAL DESIGN RESTRICTIONS (RDR); RESOLUTION ENHANCEMENT TECHNIQUES (RET);

COSTS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; PHASE SHIFT; PHOTOLITHOGRAPHY;

OPTICAL RESOLVING POWER;

EID: 2942666050     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.538242     Document Type: Conference Paper

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