A static CMOS master-slave flip-flop experiment

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2000, Pages 870-873

  Vesterbacka, Mark ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CMOS GATE; CMOS LATCHES; DEVICE GEOMETRIES; HOLD TIME; MASTER-SLAVE FLIP-FLOP; NOISE MARGINS; POWER CONSUMPTION; POWER DISSIPATION; PROPAGATION DELAYS; SET-UP TIME; SHORT PROPAGATION; SUPPLY VOLTAGES; TRANSMISSION GATE; VOLTAGE-SCALING;

FLIP FLOP CIRCUITS;

EID: 77949901515     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.913014     Document Type: Conference Paper

References (6)

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3. V. Stojanovic and V.G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems", IEEE J. Solid-State Circuits, vol.34, no.4, April 1999, pp. 536-548.
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5. Unger S.H. and Tan C.-J. "Clocking schemes for high-speed digital systems", IEEE Trans, on Computers, vol.C-35, no.10, Oct. 1986, pp. 880-895.
6. Chandrakasan A.P. and Brodersen R.W. Low-power Digital CMOS Design. Kluwer Academic Publ., 1995.