A finite-oxide thickness-based analytical model for negative bias temperature instability

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 4, 2009, Pages 537-556

  Kumar, Sanjay V ^a,b   Kim, Chris H ^b   Sapatnekar, Sachin S ^b  

^a University of Minnesota   (United States)

^b NONE

Author keywords

Delay; Frequency independence; Negative bias temperature instability (NBTI); Oxide thickness; Reaction diffusion (R D) model

Indexed keywords

ANALYTICAL MODEL; CIRCUIT DEGRADATION; DIGITAL CIRCUIT DESIGN; EXPERIMENTAL DATA; FUNCTION OF TIME; INTERFACE TRAPS; NEGATIVE BIAS TEMPERATURE INSTABILITY; OXIDE THICKNESS; PHYSICAL EFFECTS; PMOS TRANSISTORS; REACTION DIFFUSION; REACTION-DIFFUSION MODELS; RELIABLE OPERATION; TECHNOLOGY SCALING; TRAP GENERATION;

DEGRADATION; DIFFUSION IN LIQUIDS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; POLYSILICON; THERMODYNAMIC STABILITY;

NEGATIVE TEMPERATURE COEFFICIENT;

EID: 72649088516     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2009.2028578     Document Type: Conference Paper

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