Impact of negative-bias temperature instability in nanoscale SRAM array: Modeling and analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 10, 2007, Pages 1770-1781

  Kang, Kunhyuk ^a,b   Kufluoglu, Haldun ^a,b   Roy, Kaushik ^a,b   Alam, Muhammad Ashraful ^a,b  

^a IEEE

^b PURDUE UNIVERSITY   (United States)

Author keywords

Negative bias temperature instability (NBTI); Parametric failures; Reliability; SRAM

Indexed keywords

ARRAY PROCESSING; DESIGN AIDS; DIGITAL CIRCUITS; LEAKAGE CURRENTS; LSI CIRCUITS; RELIABILITY; THRESHOLD VOLTAGE; TRANSISTORS;

NANOSCALE; NEGATIVE-BIAS-TEMPERATURE-INSTABILITY (NBTI); PMOS TRANSISTORS; STATIC NOISE MARGIN; STATISTICAL READ AND WRITE STABILITY; VERTICAL OXIDE FIELD;

STATIC RANDOM ACCESS STORAGE;

EID: 34748843923     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.896317     Document Type: Article

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