Modeling and minimization of PMOS NBTI effect for robust nanometer design

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 1047-1052

  Vattikonda, Rakesh ^a   Wang, Wenping ^a   Cao, Yu ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

NBTI; Performance degradation; Reliability; Temperature; Threshold voltage; Variability

Indexed keywords

BIAS CURRENTS; MATHEMATICAL MODELS; MOS DEVICES; OPTIMIZATION; RELIABILITY ANALYSIS; THRESHOLD VOLTAGE;

NANOSCALE PMOS TRANSISTORS; NBTI; PERFORMANCE DEGRADATION; VARIABILITY;

TRANSISTORS;

EID: 34347269880     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147172     Document Type: Conference Paper

References (20)

1. International Technology Roadmap for Semiconductors, 2005.
2. N. Kimizuka, et al., "The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling," VLSI Symp. on Tech., pp. 73-74, 1999.
3. V. Reddy, et al., "Impact of negative bias temperature instability on digital circuit reliability," IRPS, pp. 248-254, 2002.
4. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, "Impact of NBTI on the temporal performance degradation of digital circuits," EDL, vol. 26, pp. 560-562, 2003.
5. H. Puchner and L. Hinh, "NBTI reliability analysis for a 90nm CMOS technology," ESSDERC, pp. 257-260, 2004.
6. A. S. Goda, G. Kapila, "Design for degradation: CAD tools for managing transistor degradation mechanisms," ISQED, pp. 416-420, 2005.
7. K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices," J. of Applied Physics, vol. 48, pp. 2004-2014, 1977.
8. D. K. Schroder, J. A. Babcock, "Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing," J. of Applied Physics, vol. 94, no. 1, pp. 1-17, July 2003.
9. S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," IRPS, pp. 273-282, 2004.
10. M. A. Alam, S. Mahapatra, "A comprehensive model of PMOS NBTI degradation," Microelectronics Reliability, vol. 45, pp. 71-81, 2005.
11. S. Ogawa and N. Shiono, "Generalized diffusion-reaction model for the low-field charge-buildup instability at the SiSiO2 interface," Physical Review B, vol. 51, no. 7, pp. 4218-4230, February 1995.
12. N. K. Jha, P. S. Reddy, and V. R. Rao, "A new drain voltage enhanced NBTI degradation mechanism," IRPS, pp. 524-528, 2005.
13. S. Rangan, N. Mielke, E. C. C. Yeh, "Universal recovery behavior of negative bias temperature instability," IEDM, pp. 341-344, 2003.
14. G. Chen, et al., "Dynamic NBTI of PMOS transistors and its impact on device lifetime," IRPS, pp. 196-202, 2003.
15. V. Huard, M. Denais, "Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in pMOS transistors," IRPS, pp. 40-45, 2004.
16. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for PMOSFETs," IEDM, pp. 345-348, 2003.
17. B. Zhu, J. S. Suehle, J. B. Bernstein, and Y. Chen, "Mechanism of dynamic NBTI of pMOSFETs," IRW, pp. 113-117, 2004.
18. W. Zhao, Y. Cao, "New generation of predictive technology model for sub-45nm design exploration," ISQED, pp. 585-590, 2006 (Available at http://www.eas.asu.edu/~ptm).
19. A. T. Krishnan, et al., "NBTI impact on transistor & circuit: models, mechanisms & scaling effects," IEDM, pp. 349-352, 2003.
20. W. Abadeer and W. Ellis, "Behavior of NBTI under AC dynamic circuit conditions," IRPS, pp. 17-22, 2003.