Trends in emerging On-chip interconnect technologies

IPSJ Transactions on System LSI Design Methodology

Volumn 1, Issue , 2008, Pages 2-17

  Pasricha, Sudeep ^a   Dutt, Nikil ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Department of Environmental and Radiological Health Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; COPPER-BASED; DEEP SUB-MICRON; DESIGN REQUIREMENTS; ELECTRICAL INTERCONNECTS; INTERCONNECT DELAY; INTERCONNECT TECHNOLOGY; MULTIPROCESSOR-SYSTEM; NETWORKS ON CHIPS; ON CHIP COMMUNICATION; ON CHIP INTERCONNECT; ON-CHIP OPTICAL INTERCONNECTS; PARASITIC RESISTANCES; PHYSICAL LEVEL; POWER DISSIPATION; PROCESS TECHNOLOGIES; RESEARCH EFFORTS; STATE OF RESEARCH; VLSI TECHNOLOGY; WIRELESS INTERCONNECTS;

CARBON NANOTUBES; COMPUTER ARCHITECTURE; COPPER; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTICAL INTERCONNECTS;

TECHNOLOGY;

EID: 70350715271     PISSN: None     EISSN: 18826687     Source Type: Journal    
DOI: 10.2197/ipsjtsldm.1.2     Document Type: Review

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