A low power, low delay TIA for on-chip applications

2005 Conference on Lasers and Electro-Optics, CLEO

Volumn 1, Issue , 2005, Pages 594-596

  Pappu, Anand M ^a   Apsel, Alyssa B ^a  

^a School of Chemical and Molecular Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOADS; MICROPROCESSOR CHIPS;

ON-CHIP APPLICATION; OPTICAL FANOUT; TIA;

ELECTRIC DELAY LINES;

EID: 30844465245     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/cleo.2005.201858     Document Type: Conference Paper

References (9)

1. G. I. Yayla, "Speed and Energy analysis of digital interconnections", A.O. vol 37, 205+ (1998)
2. A. Naeemi, "Partition length between board level electrical and optical interconnections", Proc. of the IEEE ITC. 230+ (2003)
3. C. Debaes, "Receiver-less optical clock injection for clock distribution networks", JSTQE, vol 9, (2003)
4. A. Pappu, "Electrical Isolation and Fanout in Intra-Chip Optical Interconnects", Proc. ISCAS, vol 2, 23-26, (2004)
5. H. H. Kim, "A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver", JSSC vol 36, 769-776, (2001)
6. D. Guckenberger, "A dc-coupled low-power TIA architecture for gb/s communication applications", IEEE RFICS, 515+ (2004)
7. S. M. Park, "I-Gb/s 80-dBω fully differential CMOS TIA in multichip on oxide technology", JSSC, vol39, 971-974 (2004)
8. C. Lee, "A 1.2V, 18mW, 10Gb/s SiGe Tranimpedance Amplifier", IEEE Asia-Pacific Conference on ASIC (2004)
9. Y.-H. Oh, "An inductance enhancement technique and its application to a shunt-peaked 2.5Gbps TIA" TCAS-II, (2004)