Performance constraints for onchip optical interconnects

IEEE Journal on Selected Topics in Quantum Electronics

Volumn 9, Issue 2, 2003, Pages 425-432

  Collet, J H ^a   Caignet, F ^a   Sellaye, F ^a   Litaize, D ^b  

^a LAAS CNRS   (France)

^b IRIT   (France)

Author keywords

Computer architecture; Integrated circuit; Integrated optoelectronics; Interconnections; Very large scale integration (VLSI)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED OPTOELECTRONICS; PHOTODIODES; SEMICONDUCTOR LASERS; VLSI CIRCUITS;

CLOCK TREE; ONCHIP OPTICAL INTERCONNECTS; ULTRAFAST HIGH EFFICIENCY PHOTODIODES; VERTICAL CAVITY SURFACE EMITTING LASERS;

OPTICAL INTERCONNECTS;

EID: 0242493154     PISSN: 1077260X     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSTQE.2003.812508     Document Type: Article

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