A new NBTI model based on hole trapping and structural relaxation in MOS dielectrics

IEEE Transactions on Electron Devices

Volumn 56, Issue 9, 2009, Pages 1943-1952

  Ielmini, Daniele ^a   Manigrasso, Mariaflavia ^b   Gattel, Francesco ^c   Valentini, Maria Grazia ^c  

^a POLITECNICO DI MILANO   (Italy)

^b STMICROELECTRONICS   (Italy)

^c R and D Technology Development   (Italy)

Author keywords

Charge trapping; CMOS reliability; Gatedielectric reliability; Negative bias temperature instability (NBTI); Reliability estimation; Reliability modeling

Indexed keywords

CMOS RELIABILITY; GATEDIELECTRIC RELIABILITY; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); RELIABILITY ESTIMATION; RELIABILITY MODELING;

CHARGE TRAPPING; DIELECTRIC MATERIALS; DIGITAL DEVICES; GATE DIELECTRICS; GATES (TRANSISTOR); HOLE TRAPS; MOS DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; RELIABILITY; STRUCTURAL RELAXATION;

THERMODYNAMIC STABILITY;

EID: 69549135114     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2026389     Document Type: Article

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