On-chip circuit for monitoring frequency degradation due to NBTI

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2008, Pages 532-535

  Stawiasz, Kevin ^a   Jenkins, Keith A ^a   Lu, Pong Fei ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DEGRADATION; NEGATIVE BIAS- TEMPERATURE-INSTABILITY; OPERATING VOLTAGES; RELIABILITY PHYSICS;

RELIABILITY; THERMODYNAMIC STABILITY;

DEGRADATION;

EID: 51549086781     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558941     Document Type: Conference Paper

References (8)

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2. M. Ketchen, M. Bhushan and R. Bolam, "Ring Oscillator Based Test Structure for NBTI Analysis," Proceedings of ICMTS Conference, 2007.
3. Y.-H. Lee, N. Mielke, B. Sabi, S. Stadler, R. Nachman and S. Hu, "Effect of pMOST Bias-Temperature Instability on Circuit Reliability Performance," Digest of IEDM 2003, pp 353-356.
4. S. Zafar, "Statistical Mechanics Based Model for Negative Bias Temperature Instability Induced Degradation," J. Appl. Physics 97, 2005, 103709.
5. th Annual Reliability Symposium, 2002, pp.248-254.
6. J. Keane, T.-H. Kim, C.H. Kim, "An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation," Int. Symp. Low-Power Elec. Des., 2007, pp 189-194.
7. E. Karl, P. Singh, D. Blaauw, D. Sylvester, "Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-lnstability Effect and Oxide Degradation," Proceedings of ISSCC, 2008, pp.410-411.
8. R. Fernandez, et al, "AC NBTI studied in the 1 Hz - 2GHz range on dedicated on-chip CMOS circuits, Digest of IEDM, 2006.