New insights into recovery characteristics during PMOS NBTI and CHC degradation

IEEE Transactions on Device and Materials Reliability

Volumn 7, Issue 1, 2007, Pages 130-137

  Parthasarathy, Chittoor R ^a,b   Denais, M ^a   Huard, Vincent ^c   Ribes, Guillaume ^a   Vincent, Emmanuel ^a   Bravaix, Alain ^b  

^a STMICROELECTRONICS   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

^c NXP SEMICONDUCTORS   (France)

Author keywords

Channel hot carrier (CHC); Negative bias temperature instability (NBTI); On the fly (OTF) pattern method; Recovery; Trapping

Indexed keywords

DEGRADATION; DYNAMICS; HOT CARRIERS; RECOVERY; STABILITY; THERMAL EFFECTS;

CHANNEL HOT CARRIER (CHC); NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); NONRECOVERABLE DEGRADATION; ON-THE-FLY (OTF) PATTERN METHOD;

MOS CAPACITORS;

EID: 34547226473     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.898085     Document Type: Conference Paper

References (20)

1. S. Rangan, N. Mielke, and E. C. C. Yeh, "Universal recovery behavior of negative bias temperature instability," in IEDM Tech. Dig., 2003, pp. 341-344.
2. R. Woltjer, G. M. Paulzen, H. G. Pomp, H. Lifka, P. H. Woerlee, "Three hot-carrier degradation mechanisms in deep-submicron PMOSFETs," IEEE Trans. Electron Devices, vol. 42, no. 1, pp. 109-115, Jan. 1995.
3. M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. Rey-Tauriac, and N. Revil, "On-the-fly characterization of NBTI in ultra-thin gate-oxide PMOSFETs," in IEDM Tech, Dig., 2004, pp. 109-112.
4. B. Kaczer, V. Arkhipov, R. Degraeve, N. Collaert, G. Groeseneken, and M. Goodwin, "Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification," in Proc. Int. Reliab. Phys. Symp., 2005, pp. 381-387.
5. S. Chakravarthy, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," in Proc. Int. Reliab. Phys. Symp., 2004, pp. 273-282.
6. M. A. Alam and S. Mahapatra, "A comprehensive of PMOS NBTI degradation," Microelectron. Reliab.-Special Issue (NBTI), vol. 45, no. 1, pp. 71-81, Jan. 2005.
7. C. R. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, and A. Bravaix, "New insights into recovery characteristics post NBTI stress," in Proc. Int. Reliab. Phys. Symp., 2006, pp. 471-477.
8. Y. Nissan-Cohen, J. Shappir, and D. Frohman-Bentchkowsky, "Trap generation and occupation dynamics in SiO2 under charge injection stress," J. Appl. Phys., vol. 60, no. 6, pp. 2024-2035, Sep. 15, 1986.
9. V. Huard and M. Denais, "Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors," in Proc. Int. Reliab. Phys. Symp., 2004, pp. 40-45.
10. T. L. Tewksbury, III, "Relaxation effects in MOS devices due to tunnel exchange with, near-interface oxide traps," Ph.D. dissertation, MIT, Cambridge, MA, 1992.
11. J. F. Zhang, C. Z. Zhao, A. H. Chen, and G. Groeseneken, "Holes traps in silicon dioxides: Part I & Part II," IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1267-1280, Aug. 2004.
12. P. M. Lenahan and P. V. Dressendorfer, "Hole traps and trivalent silicon centers in metal/oxide/silicon devices," J. Appl. Phys., vol. 55, no. 10, pp. 3495-3499, May 1984.
13. A. J. Lelis, T. R. Oldham, H. E. Boesch, and F. B. Mclean, "The nature of the trapped hole annealing process," IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 1808-1815, Dec. 1989.
14. D. M. Fleetwood, "Fast and slow border traps in MOS devices," IEEE Trans. Nucl. Sci., vol. 43, no. 3, pp. 779-786, Jun. 1996.
15. M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, M. Bidaud, G. Ribes, D. Barge, L. Vishnubhotla, B. Tavel, Y. Rey-Tauriac, F. Perrier, N. Revil, F. Arnaud, and P. Stolk, "New hole trapping characterization during NBTI in 65 nm node technology with distinct nitridation processing," in Proc. Integr. Reliab. Workshop, 2004, pp. 121-124.
16. C. R. Parthasarathy, M. Denais, V. Huard, G. Ribes, D. Roy, C. Guerin, F. Perrier, E. Vincent, and A. Bravaix, "Reliability of ultra thin gate oxide CMOS devices: Design perspective," in Proc. Int. Conf. IC Des. and Technol., May 2006, pp. 1-8.
17. C. Schlunder, R. Brederlow, B. Ankele, A. Lill, K. Goser, and R. Thewes, "On the degradation of P-MOSFETs in analog and RF circuits under inhomogeneous negative bias temperature stress," in Proc. Int. Reliab. Phys. Symp., 2003, pp. 5-10.
18. B. S. Doyle, B. J. Fishbein, and K. R. Mistry, "NBTI-enhanced hot carrier damage in p-channel MOSFETs," in IEDM Tech. Dig., 1991, pp. 529-533.
19. G. LaRosa, F. Guarin, S. Rauch, A. Acovic, J. Lukaitis, and E. Crabbe, "NBTI-channel hot carrier effects in PMOSFETS in advanced CMOS technologies," in Proc. Int. Reliab. Phys. Symp., 1997, pp. 282-286.
20. H. Aono, E. Murakami, K. Okuyama, K. Makabe, K. Kuroda, K. Watanabe, H. Ozaki, K. Yanagisawa, K. Kubota, and Y. Ohji, "NBT-induced hot carrier (HC) effect: Positive feedback mechanism in p-MOSFET's degradation," in Proc. Int. Reliab. Phys. Symp., 2002, pp. 79-85.