Delay correction for accurate extraction of time exponent and activation energy of NBTI

IEEE Electron Device Letters

Volumn 30, Issue 6, 2009, Pages 684-686

  Ielmini, Daniele ^a   Gattel, Francesco ^b  

^a POLITECNICO DI MILANO   (Italy)

^b R and D Technology Development   (Italy)

Author keywords

Charge trapping; CMOS reliability; Gatedielectric reliability; Negative bias temperature instability (NBTI); Reliability estimation; Reliability modeling

Indexed keywords

ANALOG APPLICATIONS; ARRHENIUS; CMOS RELIABILITY; COMPACT MODEL; DEGRADATION DATA; NEGATIVE BIAS TEMPERATURE INSTABILITY; NEGATIVE-BIAS TEMPERATURE INSTABILITY (NBTI); ON-THE-FLY; PHYSICALLY BASED MODELS; PHYSICS-BASED; PMOS TRANSISTORS; POWER LAW EXPONENT; POWER-LAW; POWER-LAW TIME DEPENDENCES; RELIABILITY ESTIMATION; RELIABILITY EXTRAPOLATION; RELIABILITY MODELING; RELIABILITY PREDICTION; TEMPERATURE KINETICS; THERMAL ACTIVATION; TIME EXPONENT;

ACTIVATION ENERGY; APPROXIMATION THEORY; CHARGE TRAPPING; ESTIMATION; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; THERMODYNAMIC STABILITY;

RELIABILITY;

EID: 67649361863     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2020308     Document Type: Article

References (12)

1. V. Huard, C. R. Parthasarathy, A. Bravaix, T. Hugel, C. Guerin, and E. Vincent, "Design-in-reliability approach for NBTI and hot-carrier degradations in advanced nodes," IEEE Trans. Electron Devices, vol. 7, no. 4, pp. 558-570, Dec. 2007.
2. H. Aono, E. Murakami, K. Shiga, F. Fujita, S. Yamamoto, M. Ogasawara, Y. Yamaguchi, K. Yanagisawa, and K. Kubota, "A study of SRAM NBTI by OTF measurements," in Proc. IEEE-IRPS, 2008, pp. 67-71.
3. V. Huard, C. Parthasarathy, C. Guerin, T. Valentin, E. Pion, M. Mammasse, N. Planes, and L. Camus, "NBTI degradation: From transistors to SRAM cells," in Proc. IRPS, 2008, pp. 289-300.
4. S. Mahapatra and M. A. Alam, "Defect generation in p-MOSFETs under negative-bias stress: An experimental perspective," IEEE Trans. Device Mater. Rel., vol. 8, no. 1, pp. 35-46, Mar. 2008.
5. Y. Mitani, M. Nagamine, H. Satake, and A. Toriumi, "NBTI mechanism in ultra-thin gate dielectric: Nitrogen-originated mechanism in SiON," in IEDM Tech. Dig., 2002, pp. 509-512.
6. J. F. Zhang, M. H. Chang, and G. Groeseneken, "Effects of measurement temperature on NBTI," IEEE Electron Device Lett., vol. 28, no. 4, pp. 298-300, Apr. 2007.
7. S. Rangam, N. Mielke, and E. C. C. Yeh, "Universal recovery behavior of negative bias temperature instability," in IEDM Tech. Dig., 2003, pp. 341-344.
8. A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, "Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2143-2154, Sep. 2007.
9. M. A. Alam, H. Kufluoglu, D. Varghese, and S. Mahapatra, "A comprehensive model for PMOS NBTI degradation: Recent progress," Microelectron. Reliab., vol. 47, no. 6, pp. 853-862, Jun. 2007.
10. 2 dynamics for negative-bias temperature-instability (NBTI) degradation," IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1101-1107, May 2007.
11. DLIN technique to study NBTI in plasma and thermal oxynitride p-MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2614-2622, Oct. 2008.
12. S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," in Proc. IEEE-IRPS, 2004, pp. 273-282.