A scaling trend of variation-tolerant SRAM circuit design in deeper nanometer era

Journal of Semiconductor Technology and Science

Volumn 9, Issue 1, 2009, Pages 37-50

  Yamauchi, Hiroyuki ^a  

^a FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Deeper nanameter; SRAM design solution; SRAM margin assist; SRAM scaling

Indexed keywords

LOGIC DESIGN; NANOTECHNOLOGY; TIMING CIRCUITS;

DESIGN SOLUTIONS; EFFECTIVE OXIDE THICKNESS; EVALUATION RESULTS; LOW STAND-BY POWER; MULTIPLE VOLTAGE; NANAMETER; SRAM DESIGN; VARIATION-TOLERANT SRAM;

INTEGRATED CIRCUIT DESIGN;

EID: 65349134252     PISSN: 15981657     EISSN: None     Source Type: Journal    
DOI: 10.5573/JSTS.2009.9.1.037     Document Type: Article

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