45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 160-161

  Ekbote, S ^a   Benaissa, K ^a   Obradovic, B ^a   Liu, S ^a   Shichijo, H ^a   Hou, F ^a   Blythe, T ^a   Houston, T W ^a   Martin, S ^a   Taylor, R ^a   Singh, A ^a   Yang, H ^a   Baldwin, G ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; POWER QUALITY; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM PROCESSES; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

AGGRESSIVE REDUCTION; ANALOG CMOS CIRCUITS; AREA SCALING; CMOS SOC; HIGH YIELDING; HIGH-QUALITY; LOW POWERS; MOBILE SYSTEMS; PASSIVE COMPONENTS; RANDOM VARIATIONS; SRAM BIT CELLS; VLSI TECHNOLOGIES;

CMOS INTEGRATED CIRCUITS;

EID: 51949095326     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588602     Document Type: Conference Paper

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