A 45nm dual-port SRAM with write and read capability enhancement at low voltage

Proceedings - 20th Anniversary IEEE International SOC Conference

Volumn , Issue , 2007, Pages 211-214

  Wang, D P ^a,b   Liao, H J ^b   Yamauchi, H ^c   Chen, Y H ^b   Lin, Y L ^b   Lin, S H ^b   Liu, D C ^b   Chang, H C ^b   Hwang, W ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL CURRENTS; DUAL-PORT; LOW POWERS;

LOGIC DESIGN; PORTS AND HARBORS; PROGRAMMABLE LOGIC CONTROLLERS;

STATIC RANDOM ACCESS STORAGE;

EID: 51049094640     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2007.4545460     Document Type: Conference Paper

References (4)

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2. M. Yamaoka, K. Osada, and K. Ishibashi, "0.4-V Logic-Library- Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array Voltage Scheme," IEEE J. Solid-State Circuits, vol.39, pp. 934-940, June 2004.
3. N. Shibata, H. Kiya, S. Kurita, H. Okamoto, M. Tan'no, and T. Douseki, "A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment - Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme," IEEE JSSC, vol. 41, 2006, p728.
4. H. Mizuno, and T. Nagano, "Driving Source-Line Cell Architecture for Sub-1-V High-Speed Low-Power Applications," IEEE JSSC, vol. 31, 1996, p552.