Embedded SRAM trend in nano-scale CMOS

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2007, Pages 19-22

  Yamauchi, Hiroyuki ^a  

^a FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; CYTOLOGY; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY;

BIT CELL; MEMORY TECHNOLOGY; PROCESS GENERATION;

STATIC RANDOM ACCESS STORAGE;

EID: 50849089591     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2007.4547608     Document Type: Conference Paper

References (7)

1. H.Yamauchi,T.Suzuki, Y.Yamagami,"A Differential Cell Terminal Biasing Scheme Enabling A Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation" IEICE Transactions on Electronics., Vol.E89-C, No.11, pp.1526-1534 (2006)
2. H.Yamauchi,T.Suzuki, Y.Yamagami," A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving Against Simultaneous Read/Write Disturbed Accesses" IEICE Transactions on Electronics., Vol. E90-C No.4, pp.1129-1137 (2007)
3. K. Zhang; U.Bhattacharya, Z. Chen; F. Hamzaoglu, D.Murray, N.Vallepalli, Y.Wang; B. Zheng; M.Bohr, "A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply", IEEE JSSC, Vol.41, No.1, pp.146-151, Jan, (2006)
4. H.Yamauchi, "Embedded SRAM Design", IEEE Asia solid state of circuits conference 2006, SRAM tutorial, Nov. (2006)
5. H.Yamauchi, T. Iwata, H.Akamatsu, A.Matsuzawa "A 0.5V Single Power Supply Operated High-Speed Boosted and Offset-Grounded Data Storage (BOGS) SRAM Cell Architecture", IEEE Transaction on VLSI Systems Vol. 5, Issue 4, pp.377-387 Dec. (1997)
6. S. Ohbayashi; M. Yabuuchi; K. Nii; Y. Tsukamoto; S. Imaoka; Y. Oda; M. Igarashi; M. Takeuchi; H. Kawashima; H. Makino; Y. Yamaguchi; K. Tsukamoto; M. Inuishi; K. Ishibashi; H. Shinohara, "A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits",IEEE Symposium on VLSI Circuits, 2-5, June, (2006)
7. D.PING Wang, H.J. Liao, H.Yamauchi, W.Hwang, Y. L. Lin, Y. H. Chen, H. C. Chang, "A 45nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage" IEEE International System on Chip Conference (SOCC), Sept. (2007)