A Disturb Decoupled Column Select 8T SRAM Cell

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 25-28

  Ramadurai, Vinod ^a   Joshi, Rajiv ^b   Kanj, Rouwaida ^c  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

8T SRAM CELLS; 90 NM TECHNOLOGY NODE; ARRAY ARCHITECTURE; CELL VOLTAGES; HARDWARE EXPERIMENT; LOW VOLTAGES; READ DISTURB; READ OPERATION;

CYTOLOGY;

EID: 84938591297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405674     Document Type: Conference Paper

References (5)

1. Y. Nakagome, M Horiguchi, T. Kawahara and K. Itoh, "Review and future prospects of low voltage RAM circuits, " IBM Journal of Research and Development, Vol. 47, No. 5/6, 2003
2. C. Wann, R. Wong, D. J. Frank, et al., " SRAM cell design for stability methodology, " 2005 IEEE VLSI-TSA International Symposium on VLSI Technology, 2005, pp 21-22.
3. R. V. Joshi, S. Mukhopadhyay, D. W. Plass, et al., "Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell, " Proceedings of the 30th European Solid-State Circuits Conference, Sept. 2004, pp 211-214
4. R. V. Joshi, 2006, "Random Access Memory with Stability Enhancement and Early Read Elimination, " United States Patent US2006/0250860 A1
5. Pilo H, et al., "An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage, " 2006 Symposium on VLSI Circuits, June 2006, pp 15-16