Low-voltage limitations of memory-rich nano-scale CMOS LSIs

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 68-75

  Itoh, Kiyoo ^a   Horiguchi, Masashi ^b   Yamaoka, Masanao ^a  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POTENTIAL; LOGIC GATES; LSI CIRCUITS;

CMOS INVERTERS; FULLY-DEPLETED (FD) SOI DEVICES; LOW-VOLTAGES; SRAM CELLS;

CMOS INTEGRATED CIRCUITS;

EID: 39549098322     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430883     Document Type: Conference Paper

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