A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 17-18

  Ohbayashi, S ^a   Yabuuchi, M ^a   Nii, K ^a   Tsukamoto, Y ^a   Imaoka, S ^b   Oda, Y ^b   Igarashi, M ^a   Takeuchi, M ^a   Kawashima, H ^a   Makino, H ^a   Yamaguchi, Y ^a   Tsukamoto, K ^a   Inuishi, M ^a   Ishibashi, K ^a   Shinohara, H ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Design   (Japan)

Author keywords

65 nm CMOS; 6T SRAM; Assist circuit; CMOS; Variability; Vth curve

Indexed keywords

BICMOS TECHNOLOGY; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

READ AND WRITE CELL STABILIZING CIRCUITS; SRAM READ AND WRITE OPERATION MARGINS;

MICROPROCESSOR CHIPS;

EID: 39749175133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Yamaoka et al., VLSI Cir. Digest, pp. 288-291, 2004.
2. Y. Tsukamoto et al., ICCAD Digest, pp. 398-405, 2005.
3. M. Yamaoka et al., ISSCC Digest, pp. 480-481, 2005.
4. K. Zhang et al., ISSCC Digest, pp. 474-475, 2005.
5. M. Kanda et al., VLSI Tech. Digest, pp. 13-14, 2003.
6. K. Utsumi et al., VLSI Tech. Digest, pp. 216-217, 2005.