An experimental 0.8 v 256-kbit SRAM macro with boosted cell array scheme

ETRI Journal

Volumn 29, Issue 4, 2007, Pages 457-462

  Chung, Yeonbae ^a   Shim, Sang Won ^b  

^a Kyungpook National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Booster; Memory; SRAM; Static noise margin

Indexed keywords

BIT ERROR RATE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL;

BOOSTERS; CELL READ-OUT CURRENTS; STATIC NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 34548049269     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.07.0106.0298     Document Type: Article

References (7)

1. K. Itoh, K. Sasaki, and Y. Nakagome, "Trends on Low-Power RAM Circuit Technologies," Proceedings of the IEEE, vol. 83, no. 4, Apr. 1995, pp. 524-543.
2. E. Seevinck, F.J. List, and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE J Solid-State Circuits, vol. SC-22, no. 5, Oct 1987, pp. 748-754.
3. H. Morimura and N. Shibata, "A Step-Down Boosted-Wordline Scheme for 1-V Battery-Operated Fast SRAM's," IEEE J. Solid-State Circuits, vol. 33, no. 8, Aug. 1998, pp. 1220-1227.
4. K. Takeda et al., "A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications," IEEE J Solid-State Circuits, vol. 41, no. 1, Jan. 2006, pp. 113-121.
5. M. Yamaoka, K. Osada, and K Ishibashi, "0.4-V Logic-Library-Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array Voltage Scheme," IEEE J Solid-State Circuits, vol. 39, no. 6, Jun. 2004, pp. 934-940.
6. K. Zhang et al., "A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," IEEE J Solid-State Circuits, vol. 41, no. 1, Jan. 2006, pp. 146-151.
7. M. Yamaoka et al., "90-nm Process-Variation Adaptive Embedded SRAM Modules with Power-Line-Floating Write Technique," IEEE J. Solid-State Circuits, vol. 41, no. 3, Mar. 2006, pp. 705-711.