Embedded SRAM circuit design technologies for a 45nm and beyond

ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Volumn , Issue , 2007, Pages 1028-1033

  Yamauchi, Hiroyuki ^a  

^a FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CELLS; CYTOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS;

6T-SRAM; AND GATES; AREA SCALING; BIT CELL; CELL CURRENTS; CELL SIZES; CIRCUIT DESIGNS; CROSS-OVER; DESIGN SOLUTIONS; EMBEDDED SRAM; FEATURE SIZES; INTERNATIONAL CONFERENCES; OPERATING VOLTAGES; PROCESS GENERATION; SCALING RATIO; STATIC-NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 48349135999     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2007.4415808     Document Type: Conference Paper

References (8)

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3. K.Zhang et.al., IEEE J. Solid State Circuits, Vol.41, No.1, pp.146-151, Jan, (2006)
4. H.Yamauchi, IEEE Asia solid state of circuits conference 2006, SRAM tutorial, Nov. (2006)
5. H.Yamauchi, et.al., IEEE Transaction on VLSI Systems Vol. 5, Issue 4, pp.377-387 Dec. (1997)
6. S.Obayashi, et.al., IEEE Symposium on VLSI Circuits, 2-5, June, (2006)
7. D.P. Wang, H.Yamauchi et.al., IEEE International System on Chip Conference (SOCC), Sept. (2007)
8. K.Osada, et.al., IEEE Solid States Circuits Conference, pp.302-303., (2003)