Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel

IEEE Transactions on Electron Devices

Volumn 51, Issue 2, 2004, Pages 212-219

  Walker, Philip M ^a   Mizuta, Hiroshi ^b,c   Uno, Shigeyasu ^b,c   Furuta, Yoshikazu ^d   Hasko, David G ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

^c JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^d OSAKA UNIVERSITY   (Japan)

Author keywords

Defect; Device simulation; Electric conductivity; Grain boundary; Moderately doped; Polysilicon; Scaling; Thin film transistor

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRONIC DENSITY OF STATES; GRAIN BOUNDARIES; POLYSILICON; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

GATE INDUCED GRAIN BARRIER; POLYSILICON THIN FILM TRANSISTOR; SILICON ON INSULATOR DEVICE; THERMAL VOLTAGE;

THIN FILM TRANSISTORS;

EID: 0442295642     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.821577     Document Type: Article

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