The impact of random doping effects on CMOS SRAM cell

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 219-222

  Cheng, B ^a   Roy, S ^a   Asenov, A ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DOPING (ADDITIVES); MOSFET DEVICES; RANDOM ACCESS STORAGE; SPURIOUS SIGNAL NOISE; STATISTICAL METHODS;

INTRINSIC PARAMETER FLUCTUATION; RANDOM DOPING EFFECTS; STATISTICAL CIRCUIT SIMULATION; SYSTEM ON CHIP (SOC);

CMOS INTEGRATED CIRCUITS;

EID: 17644391110     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. A. Asenov, et al., "Simulation of Intrinsic Parameter Fluctuations in Decananometre and Nanometer Scale MOSFETs", IEEE Trans. Elec. Dev., 50, pp. 1837-1852, 2003
3. K. Takeuchi, R. Koh, T. Mogami, "A Study of the threshold Voltage Variation for Ultra-Small Bulk and SOI CMOS", IEEE Trans. Elec. Dev., 48, pp. 1995-2001, 2001
4. A. Bhavnagarwala, X. Tang, J. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability", IEEE J. Solid-State Circuits, 36, pp. 658-665 2001
5. S. Inaba, K. Okano, S. Matsuda, et al., "High Performance 35nm Gate Length CMOS with NO Oxynitride Gate Dielectric and Ni Salicide", Tech. Digest IEDM, 2001
6. B. Cheng, S. Roy, G. Roy, A. Asenov, "Integrating 'atomistic', Intrinsic Parameter Fluctuations into Compact Model Circuit Analysis", Proc. ESSDERC 2003, pp. 437-440, 2003
7. E. Seevinck, et al, "Static-noise margin analysis of MOS SRAM cells", IEEE J. Solid-State Circuits, 22, pp. 748-754, 1987.
8. P. A. Stolk, H. P. Tuinhout, R. Duffy, et al., "CMOS device optimisation for mixed-signal technologies", Tech. Digest IEDM, 215-218, 2001