Distributed modeling of layout parasitics in large-area high-speed silicon power devices

IEEE Transactions on Power Electronics

Volumn 22, Issue 5, 2007, Pages 1847-1856

  Biondi, Tonio ^a   Greco, Giuseppe ^a   Allia, Maria Concetta ^a   Liotta, Salvatore F ^a   Bazzano, Gaetano ^a   Rinaudo, Salvatore ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

Distributed modeling; High speed; Layout parasitics; Power devices; Silicon technology

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENT DISTRIBUTION; MATHEMATICAL MODELS; MOSFET DEVICES; SEMICONDUCTING SILICON; SWITCHING FREQUENCY;

LAYOUT PARASITICS; SILICON POWER DEVICES; SILICON TECHNOLOGY;

POWER ELECTRONICS;

EID: 34548810850     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2007.904241     Document Type: Article

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