Charge-control modeling of power bipolar junction transistors

IEEE Transactions on Power Electronics

Volumn 15, Issue 6, 2000, Pages 1072-1080

  Vijayalakshmi, Ramachandran ^a,b   Trivedi, Malay ^a,c   Shenai, Krishna ^a,c  

^a IEEE

^b INTEL CORPORATION   (United States)

^c University of Illinois   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CHARGE; ELECTRIC POTENTIAL; SEMICONDUCTOR DEVICE MODELS; SWITCHING;

CHARGE DECAY; CIRCUIT SIMULATOR; LUMPED CIRCUIT; POWER BIPOLAR JUNCTION TRANSISTORS; QUASISATURATION MODEL;

BIPOLAR TRANSISTORS;

EID: 0034313571     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/63.892821     Document Type: Article

References (18)

1. M. S. Adler, K. W. Owyang, B. J. Baliga, and R. A. Kokosa, "The evolution of power device technology," IEEE Trans. Electron Devices, vol. ED-31, pp. 1570-1591, Nov. 1984.
2. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design. New York: Wiley, 1996.
3. P. L. Hower and V. G. K. Reddi, "Avalanche breakdown in transistors," IEEE Trans. Electron Devices, vol. ED-17, pp. 320-335, Mar. 1970.
4. I. Widjaja, A. Kurnia, K. Shenai, and D. M. Divan, "Switching dynamics of IGBTs in soft-switching converters," IEEE Trans. Electron Devices, vol. 42, pp. 445-454, Mar. 1995.
5. G. M. Kull, L. W. Nagel, S. W. Lee, P. Lloyd, E. J. Prendergast, and H. Dirks, " A unified model for bipolar transistor including quasisaturation effect," IEEE Trans. Electron Devices, vol. ED-32, pp. 1103-1113, June 1985.
6. C. McAndrew, J. Seitchik, D. Bowers, M. Foisy, I. Getreu, M. Mc-Swam, S. Moinian, J. Parker, P. V. Wijnen, and L. Wagner, "VBIC95: An improved vertical, IC bipolar transistor model," in Proc. IEEE Bipolar/BiCMOS Ckts. Tech. Mtg. (BCTM), 1995, pp. 170-177.
7. S. A. Smithies and K. F. Poole, "A graphical model for two region saturation in bipolar transistors and its implementation in the modeling program SPICE," IEEE J. Solid State Circuits, vol. SC-22, pp. 301-307, Feb. 1987.
8. P. Leturcq, "Power semiconductor device modeling dedicated to circuit simulation," in Proc. IEEE Int. Symp. Power Semic. Devices ICs (ISPSD), 1999, pp. 19-26.
9. M. Trivedi, "Modeling the Bipolar Transistor for SPICE," Magnetek, Int. Rep., 1996.
10. K. Shenai, " Mixed-mode circuit simulation: An emerging CAD tool for the design and optimization of power semiconductor devices and circuits," in Proc. IEEE 1994 4th PELS Wksp. Comput. Power Electron., 1994, pp. 1-5.
11. ATLAS Users Manual. Santa Clara, CA: Silvaco International, 1998.
12. SABER Users Manual. Beaverton, OR: Analogy, Inc., 1998.
13. PSPICE Users Manual, Microsim Corporation.
14. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
15. I. E. Getreu, Modeling the Bipolar Transistor. Beaverton, OR: Tektronix Inc., 1976.
16. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE. New York: McGraw-Hill, 1993.
17. S. Pendharkar, C. Winterhalter, M. Trivedi, H. Li, A. Kurnia, D. Divan, and K. Shenai, "Test circuits for verification of power device models," in Proc. IEEE IAS, 1995, pp. 1055-1060.
18. R. Vijayalakshmi, M. Trivedi, and K. Shenai, "Power bipolar transistor performance in hard- and soft-switching power converters," in Proc. IEEE IAS Ann. Mtg., 1998, pp. 888-892.