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Volumn 48, Issue 11, 2001, Pages 2544-2550

Reverse bias instabilities in bipolar power transistors with cellular layout

Author keywords

Bipolar; Drive circuits; Failure analysis; Impact ionization; IMPATT diodes; Nondestructive testing; Power bipolar transistors; Power semiconductor devices; Power transistors; Second breakdown; Semiconductor device modeling; Semiconductor device testing; Simulation; Transistors

Indexed keywords

CAPACITANCE; ELECTRIC CHARGE; ELECTRIC FIELD EFFECTS; FAILURE ANALYSIS; IMPACT IONIZATION; IMPATT DIODES; INTEGRATED CIRCUIT LAYOUT; NONDESTRUCTIVE EXAMINATION; OSCILLATIONS; POWER ELECTRONICS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING;

EID: 0035507070     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.960380     Document Type: Article
Times cited : (2)

References (20)
  • 9
    • 0006738728 scopus 로고
    • Semiconductor measurement technology: A programmable reverse-bias safe operating area transistor tester
    • NIST Spec. Publ. 400-87
    • (1990)
    • Berning, D.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.