Efficient test solutions for core-based designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 5, 2004, Pages 758-775

  Larsson, Erik ^a,b   Arvidsson, Klas ^a   Fujiwara, Hideo ^b   Peng, Zebo ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Scan chain partitioning; System on chip (SOC) testing; Test access mechanism design; Test data transportation; Test scheduling; Test solutions

Indexed keywords

COMPUTATIONAL METHODS; COSTS; DATA REDUCTION; ENERGY UTILIZATION; ITERATIVE METHODS; OPTIMIZATION; SCHEDULING;

SCAN-CHAIN PARTITIONING; SYSTEM-ON-CHIP (SOC) TESTING; TEST ACCESS MECHANISM DESIGN; TEST DATA TRANSPORTATION; TEST SCHEDULING; TEST SOLUTIONS;

MICROPROCESSOR CHIPS;

EID: 2542459381     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.826560     Document Type: Article

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