Power constrained preemptive TAM scheduling

Proceedings of the European Test Workshop

Volumn 2002-January, Issue January, 2002, Pages 119-126

  Larsson, Erik ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUIT TESTING; SCHEDULING ALGORITHMS; TESTING;

BIN PACKING PROBLEM; ITS EFFICIENCIES; OPTIMAL SOLUTIONS; POWER CONSTRAINTS; SCAN CHAIN PARTITIONING; SCHEDULING PROBLEM; SCHEDULING PROCESS; TEST ACCESS MECHANISM;

SCHEDULING;

EID: 84931351424     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2002.1029648     Document Type: Conference Paper

References (21)

1. J. Aerts and E. J. Marinissen, "Scan Chain Design for Test Time Reduction in Core-Based ICs", Proceedings of IEEE International Test Conference (ITC), pp. 448-457, Washington, DC, October 1998.
2. M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits", Kluwer Academic Publ., ISBN 0-7923-7991-8.
3. K. Chakrabarty, "Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming", IEEE Transactions on CAD of IC and Systems., Vol. 19, No. 10, pp. 1163-1174, Oct. 2000.
4. R. Chou et al., "Scheduling Tests for VLSI Systems Under Power Constraints", IEEE Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
5. T. Cormen, C. Leiserson, and R. Rivest, "Introduction To Algorithms", The MIT Press, ISBN 0-262-03141-8, 1989.
6. S. Gerstendörfer and H-J Wunderlich, "Minimized Power Consumption for Scan-Based BIST", Proceedings of IEEE International Test Conference (ITC), pp. 77-84, Atlantic City, NJ, Sep. 1999.
7. Y. Huang et al., "Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design", Proceedings of IEEE Asian Test Symposium (ATS), pp. 265-270, Kyoto, Japan, Nov. 2001.
8. V. Iyengar and K. Chakrabarty, "Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip", Proceedings of IEEE VLSI Test Symposium (VTS), pp. 42-47, CA, April 2001.
9. V. Iyengar et al., "Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip", Proceedings of IEEE International Test Conference (ITC), pp. 1023-1032, Baltimore, MD, Nov. 2001.
10. ITĆ02 (International Test Conference) SOC Benchmarks, http://www.extra.research.philips.com/itc02socbenchm/.
11. S. Koranne, "Design of Reconfigurable Access Wrappers for Embedded Core Based SOC Test", Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp 106-111, San Jose, California, March 2002.
12. E. Larsson and Z. Peng, "An Integrated System-On-Chip Test Framework", Proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 138-144, Munchen, Germany, March 2001.
13. E. Larsson and Z. Peng, "The Design and Optimization of SOC Test Solutions", Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 523-530, San Jose, CA, Nov. 2001.
14. E. Larsson and Z. Peng, "Test Scheduling and Scan-Chain Division Under Power Constraint", Proc. of IEEE Asian Test Symposium (ATS), pp. 259-264, Kyoto, Japan, Nov. 2001.
15. E. J. Marinissen et al., "A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores", Proceedings of IEEE International Test Conference (ITC), pp. 284-293, Washington, DC, Oct. 1998.
16. E. J. Marinissen et al., "Towards a Standard for Embedded Core Test: An Example", Proc. of IEEE International Test Conference (ITC), pp. 616-627, Atlantic City, NJ, Sep. 1999.
17. E. J. Marinissen et al., "Wrapper Design for Embedded Core Test", Proceedings of IEEE International Test Conference (ITC), pp. 911-920, Atlantic City, NJ, Oct. 2000.
18. V. Muresan et al., "A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling", Proceedings of IEEE International Test Conference (ITC), pp. 882-891, Atlantic City, NJ, Oct. 2000.
19. N. Nicolici and B. M. Al-Hashimi, "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths", Proceedings of IEEE International Test Conference (ITC), pp. 662-671, Atlantic City, NJ, Oct. 2000.
20. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices", Proceedings of IEEE VLSI Test Symposium (VTS), pp. 4-9, Atlantic City, NJ, April 1993.
21. J. Saxena et al., "An Analysis of Power Reduction Techniques in Scan Testing", Proceedings of IEEE International Test Conference (ITC), pp. 670-677, Baltimore, MD, Oct. 2001.