Design and optimization of multi-level TAM architectures for hierarchical SOCs

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 299-304

  Iyengar, V ^a   Chakrabarty, K ^b   Krasniewski, M D ^b   Kumar, G N ^b  

^a IBM   (United States)

^b USA   (United States)

Author keywords

Benchmark testing; Computer architecture; Costs; Design engineering; Design optimization; Embedded computing; Logic testing; Microelectronics; System testing; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER TESTING; COST ENGINEERING; COSTS; DESIGN; EMBEDDED SYSTEMS; MICROELECTRONICS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

BENCHMARK TESTING; DESIGN ENGINEERING; DESIGN OPTIMIZATION; EMBEDDED COMPUTING; LOGIC TESTING; SYSTEM ON A CHIP; SYSTEM TESTING;

INTEGRATED CIRCUIT DESIGN;

EID: 84943543788     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197667     Document Type: Conference Paper

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