On the use of k - tuples for SoC test schedule representation

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 539-548

  Koranne, Sandeep ^a   Iyengar, Vikram ^b  

^a Tanner Research Inc   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER SIMULATION; COST EFFECTIVENESS; OPTIMIZATION; SCHEDULING; SEMICONDUCTOR DEVICE MANUFACTURE;

AUTOMATIC TEST EQUIPMENT; SILICON ON CHIP TEST SCHEDULE; TEST ACCESS MECHANISM;

SEMICONDUCTOR DEVICE TESTING;

EID: 0036446699     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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