The design and optimization of SOC test solutions

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 523-530

  Larsson, E ^a   Peng, Z ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; LINEAR PROGRAMMING; OPTIMIZATION; SIMULATED ANNEALING;

SYSTEM ON CHIP (SOC);

INTEGRATED CIRCUIT TESTING;

EID: 0035209105     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. A high-level EDa environment for the automatic insertion of HD-BIST structures
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5. A distributed BIST control scheme for complex VLSI devices
6. Scheduling tests for VLSI systems under power constraints
7. A comparison of classical scheduling approaches in power-constrained block-test scheduling
8. Optimization by simulated annealing
9. Minimized power consumption for scan-based BIST
10. An ILP formulation to optimize test access mechanisms in system-on-a-chip testing
11. Optimal test access architectures for system-on-a-chip
12. Design of system-on-a-chip test access architectures using integer linear programming
13. Design of system-on-a-chip test access architecture under place-and-route and power constraints
14. Scan chain design for test time reduction in core-based ICs
15. A structured and scalable mechanism for test access to embedded reusable cores
16. Towards a standard for embedded core test: An example
17. Wrapper design for embedded core test