Effective and efficient test architecture design for SOCs

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 529-538

  Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

HEURISTIC ALGORITHM; SYSTEM ON CHIP TESTING;

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

INTEGRATED CIRCUIT TESTING;

EID: 0036444568     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2002.1041803     Document Type: Conference Paper

References (19)

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2. Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. ITC'02 SOC Test Benchmarks Web Sites. http://www.extra.research.philips.com/itc02socbench/.
3. Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proceedings IEEE International Test Conference (ITC), Baltimore, MD, October 2002.
4. Joep Aerts and Erik Jan Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proceedings IEEE International Test Conference (ITC), pages 448-457, Washington, DC, October 1998.
5. Prab Varma and Sandeep Bhatia. A Structured Test Re-Use Methodology for Core-Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 294-302, Washington, DC, October 1998.
6. Erik Jan Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, October 1998.
7. Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming. In Proceedings IEEE VLSI Test Symposium (VTS), pages 127-134, Montreal, Canada, April 2000.
8. Zahra sadat Ebadi and Andre Ivanov. Design of an Optimal Test Access Architecture Using a Genetic Algorithm. In Proceedings IEEE Asian Test Symposium (ATS), pages 205-210, Kyoto, Japan, November 2001.
9. Krishnendu Chakrabarty. Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 432-437, Los Angeles, CA, June 2000.
10. Yu Huang et al. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. In Proceedings IEEE Asian Test Symposium (ATS), pages 265-270, Kyoto, Japan, November 2001.
11. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. In Proceedings IEEE International Test Conference (ITC), pages 1023-1032, Baltimore, MD, October 2001.
12. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores. Journal of Electronic Testing: Theory and Applications, 18(2):213-230, April 2002.
13. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Efficient Wrapper/TAM Co-Optimization for Large SOCs. In Proceedings Design, Automation, and Test in Europe (DATE), pages 491-498, Paris, France, March 2002.
14. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. In Proceedings IEEE VLSI Test Symposium (VTS), pages 253-258, Monterey, CA, April 2002.
15. Vikram Iyengar, Krishnendu Chakrabarty, and Erik Jan Marinissen. Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages 685-690, New Orleans, LO, June 2002.
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18. R.L. Graham. Bounds on Multiprocessing Anomalies. SIAM Journal of Applied Mathematics. 17:416-429, 1969.
19. Erik Jan Marinissen, Sandeep Kumar Goel, and Maurice Lousberg. Wrapper Design for Embedded Core Test. In Proceedings IEEE International Test Conference (ITC), pages 911-920, Atlantic City, NJ, October 2000.