An integrated framework for the design and optimization of SOC test solutions

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 18, Issue 4-5, 2002, Pages 385-400

  Larsson, Erik ^a   Peng, Zebo ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Power consumption; SOC test; Test access mechanism design; Test conflicts; Test resource partitioning; Test resource placement; Test scheduling

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DESIGN FOR TESTABILITY; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; SCHEDULING; SIMULATED ANNEALING;

POWER CONSUMPTION; SYSTEM ON CHIP; TEST ACCESS MECHANISM DESIGN; TEST RESOURCE PARTITIONING; TEST RESOURSE PLACEMENT; TEST SCHEDULING;

INTEGRATED CIRCUIT TESTING;

EID: 0036693122     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1016589322936     Document Type: Article

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