Test scheduling and test access architecture optimization for system-on-chip

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 411-416

  Hsu, Huan Shan ^a   Huang, Jing Reng ^a   Cheng, Kuo Liang ^a   Wang, Chih Wea ^a   Huang, Chih Tsun ^a   Wu, Cheng Wen ^a   Lin, Youn Long ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b Global Unichip   (Taiwan)

Author keywords

Algorithm design and analysis; Computer architecture; Cost function; Hip; Laboratories; Multimedia systems; Processor scheduling; Read only memory; System testing; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COST FUNCTIONS; HARDWARE; HEURISTIC ALGORITHMS; HOT ISOSTATIC PRESSING; LABORATORIES; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; ROM; SCHEDULING;

ALGORITHM DESIGN AND ANALYSIS; PROCESSOR SCHEDULING; RESOURCE CONSTRAINT; SYSTEM INTEGRATORS; SYSTEM ON A CHIP; SYSTEM TESTING; TEST ACCESS ARCHITECTURE; TEST ACCESS MECHANISM;

SYSTEM-ON-CHIP;

EID: 84883368021     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181746     Document Type: Conference Paper

References (16)

1. Y. Zorian, E. J. Marinissen, and S. Dey. Testing embeddedcore based system chips. In Proc. Int. Test Conf. (ITC), pages 130-143, Oct. 1998.
2. C.-W. Wu, J.-F. Li, and C.-T. Huang. Core-based system-onchip testing: Challenges and opportunities. J. Chinese Institute of Electrical Engineering, 8(4):335-353, Nov. 2001.
3. IEEE. IEEE P1500 standard for embedded core test (SECT). http://grouper.ieee.org/groups/1500/, 2002.
4. J. Aerts and E. J. Marinissen. Scan chain design for test time reduction in core-based ICs. In Proc. Int. Test Conf. (ITC), pages 448-457, 1998.
5. E. J. Marinissen, R. Arendsen, and G. Bos. A structured and scalable mechanism for test access to embedded reusable cores. In Proc. Int. Test Conf. (ITC), pages 284-293, 1998.
6. L. Whetsel. Addressable test ports-an approach to testing embedded cores. In Proc. Int. Test Conf. (ITC), pages 1055-1061, 1999.
7. M. Benabdenbi, W. Maroufi, and M. Marzouki. Testing TAPed cores and wrapped cores with the same test access mechanism. In Proc. Design, Automation and Test in Europe (DATE), pages 150-155, Munich, Mar. 2001.
8. R. M. Chou, K. K. Saluja, and V. D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, 5(2):175-185, June 1997.
9. K. Chakrabarty. Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 19(10):1163-1174, Oct. 2000.
10. V. Iyengar and K. Chakrabarty. Precedence-based, preemptive, and power-constrained test scheduling for system-on-achip. In Proc. IEEE VLSI Test Symp. (VTS), pages 368-374, 2001.
11. V. Iyengar, K. Chakrabarty, and E. J. Marinissen. Test wrapper and test access mechanism co-optimzation for system-onchip. In Proc. Int. Test Conf. (ITC), pages 1023-1032, Baltimore, Oct. 2001.
12. V. Iyengar, K. Chakrabarty, and E. J. Marinissen. Test wrapper and test access mechanism co-optimization for systemon-chip. J. Electronic Testing: Theory and Application, 18(2):213-230, Apr. 2002.
13. C.-P. Su and C.-W. Wu. Graph-based power-constrained test scheduling for SOC. In Proc. IEEE Int. Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 61-68, Brno, Czech Republic, Apr. 2002. (Best Paper Award).
14. V. Iyengar, K. Chakrabarty, and E. J. Marinissen. On using rectangle packing for SOC wrapper/TAM co-optimization. In Proc. IEEE VLSI Test Symp. (VTS), pages 253-258, Monterey, Apr. 2002.
15. C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu, and Y.-L. Lin. A test access control and test integration system for system-on-chip. In Sixth IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), pages P21-P28, Monterey, California, May 2002.
16. E. J. Marinissen, V. Iyengar, and K. Chakrabarty. ITC'02 SOC test benchmarks. http://www.extra.research.philips.com/itc02socbenchm/, 2002.