Test scheduling of BISTed memory cores for SoC

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 356-361

  Wang, Chih Wea ^a   Huang, Jing Reng ^a   Lin, Yen Fu ^a   Cheng, Kuo Liang ^a   Huang, Chih Tsun ^a   Wu, Chen Wen ^a   Lin, Youn Long ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b Global Unichip   (Taiwan)

Author keywords

Automatic testing; Built in self test; Circuit testing; Job shop scheduling; Logic testing; Minimization; Power system reliability; Scheduling algorithm; Sequential analysis; System testing

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; INTEGRATED CIRCUITS; JOB SHOP SCHEDULING; OPTIMIZATION; RELIABILITY ANALYSIS; SCHEDULING; SCHEDULING ALGORITHMS; SEMICONDUCTOR DEVICE MANUFACTURE; SIMULATED ANNEALING; SYSTEM-ON-CHIP;

CIRCUIT TESTING; LOGIC TESTING; POWER SYSTEM RELIABILITY; SEQUENTIAL ANALYSIS; SYSTEM TESTING;

BUILT-IN SELF TEST;

EID: 0347498780     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181737     Document Type: Conference Paper

References (14)

1. A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, and M. Lobetti-Bodorni. A programmable BIST architecture for clusters of multiple-port SRAMs. In Proc. Int. Test Conf. (ITC), pages 557-566, 2000.
2. A. Bommireddy, J. Khare, S. Shaikh, and S. Su. Test and debug of networking socs-a case study. pages 121-126, Montreal, Apr. 2000.
3. K. Chakrabarty. Design of system-on-a-chip test access architecture under place-and-route and power constraints. In Proc. IEEE/ACM Design Automation Conf. (DAC), pages 432-437, 2000.
4. K. Chakrabarty. Design of system-on-a-chip test access architecture using integer linear programming. In Proc. IEEE VLSI Test Symp. (VTS), pages 127-134, 2000.
5. K. Chakrabarty. Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 19(10):1163-1174, Oct. 2000.
6. R.M. Chou, K. K. Saluja, and V. D. Agrawal. Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Systems, 5(2):175-185, June 1997.
7. G. L. Craig, C. R. Kime, and K. K. Saluja. Test scheduling and control for VLSI built-in self-test. IEEE Trans. Computers, 37(9):1099-1109, Sept. 1988.
8. S. H. Gerez. Algorithms for VLSI Design Automation. John Wiley & Sons Ltd., New York, NJ, USA, 1998.
9. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang. A programmable BIST core for embedded DRAM. IEEE Design & Test of Computers, 16(1):59-70, Jan.-Mar. 1999.
10. V. Iyengar, K. Chakrabarty, and E. J.Marinissen. Test wrapper and test access mechanism co-optimzation for system-on-chip. In Proc. Int. Test Conf. (ITC), pages 1023-1032, Baltimore, Oct. 2001.
11. S. Kirkpatrick, C. Gelatt, and M. Vecchi. Optimization by simulated annealing. In Science, pages 671-690, May 1983.
12. C. P. Ravikumar, A. Verma, and G. Chandra. A polynomialtime algorithm for power constrained testing of core based systems. pages 107-112, Shanghai, Nov. 1999.
13. C.-W. Wang, R.-S. Tzeng, C.-F. Wu, C.-T. Huang, C.-W. Wu, S.-Y. Huang, S.-H. Lin, and H.-P. Wang. A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters. In Proc. Tenth IEEE Asian Test Symp. (ATS), pages 103-108, Kyoto, Nov. 2001.
14. Y. Zorian. A distributed BIST control scheme for complex VLSI devices. In Proc. IEEE VLSI Test Symp. (VTS), pages 4-9, 1993.