An efficient test vector compression scheme using selective huffman coding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 6, 2003, Pages 797-806

  Jas, Abhijit ^a,b   Ghosh Dastidar, Jayabrata ^a,c   Ng, Mom Eng ^a,d   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

^b INTEL CORPORATION   (United States)

^c ALTERA CORPORATION   (United States)

^d ADVANCED MICRO DEVICES   (United States)

Author keywords

Automatic test equipment; Compression; Decompression architecture; Embedded core testing; Test set encoding; Testing time

Indexed keywords

BANDWIDTH; DATA COMPRESSION; DECODING; DIGITAL STORAGE; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MANUFACTURE; VECTORS;

HUFFMAN CODING;

SIGNAL ENCODING;

EID: 0037704218     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.811452     Document Type: Conference Paper

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