Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 145-149

  Chandra, A ^a   Chakrabarty, K ^a  

^a Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; COMPRESSION METHODS; CORE UNDER TESTS; EMBEDDED CORES; GOLOMB CODING; SCAN CHAIN; SYSTEM-ON-A-CHIP; TEST DATA COMPRESSION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EXHIBITIONS; INTEGRATED CIRCUIT TESTING;

DATA COMPRESSION;

EID: 84893648051     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915015     Document Type: Conference Paper

References (11)

1. Y. Zorian, E. J. Marinissen and S. Dey, "Testing embeddedcore based system chips", Proc. Int. Test Conf., pp. 130-143, 1998.
2. V. Iyengar, K. Chakrabarty and B. T. Murray, "Deterministic built-in pattern generation for sequential circuits", JETTA, vol. 15, pp. 97-115, August/October, 1999.
3. A. Jas and N. A. Touba, "Test vector decompression via cyclical scan chains and its application to testing corebased design", Proc. Int. Test Conf., pp. 458-464, 1998.
4. I. Hamzaoglu and J. H. Patel, "Test set compaction algorithms for combinational circuits", Proc. Int. Conf. CAD, pp. 283-289, 1998.
5. S. W. Golomb, "Run-length encoding", IEEE Trans. Inf. Theory, vol. 1T-12, pp. 399-401, 1966.
6. H. Kobayashi and L. R. Bahl, "Image data compression by predictive coding, Part I: Prediction Algorithm", IBM Journal of R&D, vol. 18, pp. 164, 1974.
7. A. Chandra and K. Chakrabarty, "Test data compression for system-on-a-chip using Golomb codes", Proc. IEEE VLSI Test Symp., pp. 113-120, 2000.
8. A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures based on Golomb codes", IEEE Trans. CAD, vol. 20, March 2001 (accepted for publication).
9. H. K. Lee and D. S. Ha, "An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation", Proc. Int. Test Conf, pp. 946-955, 1991.
10. D. Heidel, S. Dhong, P. Hofstee, M. Immediate K. Nowka, J. Silberman and K. Stawiasz. "High-speed serialiazing/deserializing design-for-test methods for evaluating a 1 GHz microprocessor", Proc. IEEE VLSI Test Symp., pp. 234-238, 1998.
11. H. K. Lee and D. S. Ha. "On the Generation of Test Patterns for Combinational Circuits" Tech. Report No. 12.93, Dept. Electrical Eng., Virginia Poly. Inst, and State Univ.